A programmable counter is a digital device which stores a number and increments or decrements that number on command. Such counters can supply a signal when the number stored within the counter reaches a certain value. In addition, such counters are able to supply the number stored within to other devices via a parallel output data path. The counter of the subject is embedded in a very large scale integrated ("VLSI") device and, as such, is relatively inaccessible to typical test apparatus (e.g. logic probes).
Following manufacture or during operation, these counters within the VLSI device may malfunction, resulting in an inability to store or count in the desired manner. Therefore, it becomes essential to test all bits of the counter to determine whether any design or fabrication errors or faults exist therein.
Classically, in an n-bit binary counter, there are 2.sup.n states or numbers which can be represented in the counter. Accordingly, prior art counter testing methods included those which test the counter by forcing it to assume sequentially each of the 2.sup.n states. These methods were extremely time consuming and repetitious. Therefore, there has been a quest to find more efficient and expeditious methods for testing an n-bit counter.
One such method is described in U.S. Pat. No. 4,661,930, which issued on Apr. 28, 1987 to Tran, directed to a register of the type used as an address counter in a dynamic RAM. The counter is tested by a method which does not require cycling through every possible value of the registered contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a 1-bit output which is monitored off-chip. Then, a carry feedback path to the counter register is altered, as by inverting all but the least significant bit, and the contents again checked, using the 1-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.
Tran shows a method for testing an n-bit counter in three steps, regardless of the number of bits in the counter.
However, Tran requires construction of an external apparatus to check the counter, namely an apparatus which includes AND and OR gates, a signal inverter and a counter decoder. Although this apparatus allows the test to be performed in only three cycles, it is complex and relatively costly.
It is desired to test an n-bit counter in the least time while achieving the maximum level of assurance as to the accuracy and completeness of the test ("fault coverage"). It is also desired to test the counter without requiring external hardware components.
The subject invention, therefore, was developed to allow an n-bit counter to be tested in n+1 cycles, without requiring external hardware components. The subject invention is designed to allow the counter to be tested as part of an initialization routine performed during startup (power-up) in its operating environment.